The present invention relates to a semiconductor integrated circuit having nonvolatile memory cells each having a threshold voltage which can be changed reversibly by electrical erasing and writing and, more particularly to a technology for suppressing the over-erasing of the nonvolatile memory cell.
The foregoing nonvolatile memory cell has an erased state and a written state. The erased state is, e.g., a state in which a threshold voltage viewed from the select terminal of the memory cell is low and the written state is, e.g., a state in which the threshold voltage viewed from the select terminal of the memory cell is high. The select terminal of the nonvolatile memory cell is connected to a word line and an erase operation which lowers the threshold voltage of the nonvolatile memory cell is performed with respect to each of the memory cells connected to a selected word line. In the case of a nonvolatile memory cell having, e.g., a floating gate structure, a high voltage is applied to a word line so that electrons accumulated in the floating gate are released toward a source line or a substrate (a well region). At this time, there are often cases where a memory cell having a fast erase characteristic is in a depleted state (over-erased state) when the threshold voltage of a memory cell having a slowest erase characteristic reaches an erase verify level due to the different erase characteristics of the individual memory cells. After the threshold voltage of each of the memory cells connected to the selected word line reaches the erase verify level or lower, the process (write-back process) of rendering uniform the lower limit of the erase distribution by performing selective writing to each of memory cells having a threshold voltage not higher than the objective lower limit of the erase distribution. By performing this process, the depleted state is eliminated. Thus, the erase operation consists of two processes which are the process of lowering the threshold voltage (erase process) and the process (write-back process) of rendering uniform the lower limit of the threshold voltage distribution.
As a technology for preventing over-erasing, Patent Document 1 provides a control sequence which performs, after the erase operation, a leak check for detecting that the total sum of leakage currents in all the memory cells connected to a selected bit line is not more than a specified level, performs weak writing to each of the memory cells in an over-erased state by temporarily halting the erase operation when the result of the leak check is not OK, and returns to the erase operation.
[Patent Document 1] Japanese Unexamined Patent Publication No. 2000-260189